An integrated circuit package generally comprises a substrate made of epoxy impregnated fiberglass material, an integrated circuit made of silicon, and an encasing material that surrounds delicate electrical elements to protect them from mechanical damage and environmental exposure. During the manufacture of an integrated circuit package, the integrated circuit portion is generally referred to as an integrated circuit die.
There are certain manufacturing processes for an integrated circuit package (e.g., transfer molding of an exposed integrated circuit die) that require the integrated circuit die to be clamped. In these types of processes it is highly desirable that the integrated circuit die be located accurately in three dimensions. It is also highly desirable that the accurate three dimensional location of the integrated circuit die be repeatable.
The alignment of an integrated circuit die on a substrate is normally considered to be acceptable if the integrated circuit die is placed in its intended position within a tolerance of approximately one hundred microns (100 μm).
The placement of an integrated circuit die on the surface of the substrate may be considered as a problem of aligning the integrated circuit die within a conventional three dimensional rectangular coordinate system comprising an X-axis, a Y-axis and a Z-axis. The X-axis and the Y-axis form a plane that is coincident with the surface of the substrate. The Z-axis is perpendicular to the plane formed by the X-axis and the Y-axis. The value of Z represents the vertical location of the integrated circuit die with respect to the plane surface of the substrate.
To be within the normally acceptable tolerance of one hundred microns (100 μm), the location of the integrated circuit die on the substrate with respect to the X-axis must be within plus or minus one hundred microns (100 μm) of the intended X position. Similarly, the location of the integrated circuit die on the substrate with respect to the Y-axis must be within plus or minus one hundred microns (100 μm) of the intended Y position. Lastly, the location of the integrated circuit die on the substrate with respect to the Z-axis must be within a range of plus or minus twenty five microns (25 μm) to plus or minus fifty microns (50 μm) of the intended Z position.
In addition, the angular alignment of an integrated circuit die on a substrate must be accurate. Assume that the correct angular placement of an integrated circuit die is with a first side parallel to the X-axis and with a second side parallel to the Y-axis. If the integrated circuit die is not correctly aligned in its angular position, then it will be in a rotated position with respect to its correct angular position.
Similarly, it is possible for an integrated circuit die to be angularly misaligned with respect to the vertical Z-axis. Assume that the correct angular placement of an integrated circuit die is for the bottom of the integrated circuit die to be parallel with the surface of the substrate. Then the plane of the bottom of the integrated circuit die is to be perpendicular to the Z-axis. If the bottom of the integrated circuit die is inclined or tilted with respect to the surface of the substrate, then the integrated circuit die will not be in its correct angular position with respect to the vertical Z-axis.
In silicon sensor applications part of the silicon surface of the integrated circuit die is exposed and is not covered by a protective molding. In silicon sensor applications the position of the integrated circuit die must be precisely located with respect to the X, Y, and Z axes in order to have an acceptable yield after the molding process has been performed. That is, in order to improve the yield in silicon sensor applications the tolerance of the location of the integrated circuit die on the substrate must be minimized. This requires minimizing the variations in the X, Y and Z locations of the integrated circuit die, minimizing the angular rotation of the integrated circuit die in the X-Y plane, and minimizing the angular tilt of the integrated circuit die with respect to the Z-axis.
When an integrated circuit substrate is manufactured tooling holes are drilled in the surface of the substrate. Then a copper pattern is etched in the substrate using photolithography techniques. The alignment of the copper pattern measured with respect to the position of the tooling holes is within a tolerance of one hundred microns (100 μm). The misalignment of the copper pattern with a respect to the tooling holes that are represented by the tolerance of one hundred microns (100 μm) is due to the accumulation of conventional manufacturing tolerances during the manufacturing process. The misalignment is due in part to alignment errors between the mask used to etch the copper pattern and the tooling holes on the substrate.
During the placement of the integrated circuit die on the substrate, optical alignment is used to place the integrated circuit die with respect to certain fiducial reference points that are created in the etched copper pattern on the substrate. The fiducial reference points may be misaligned with respect to the tooling holes by as much as one hundred microns (100 μm). This misalignment is a major source of error in the placement of an integrated circuit die.
An epoxy based glue is first applied to the substrate before the integrated circuit die is placed into position. The integrated circuit die is then placed in contact with the epoxy based glue. After the integrated circuit die has been placed into position, the substrate is heated for one to two hours in order to cure the epoxy based glue and solidify the bond between the integrated circuit die and the substrate.
During the curing process the integrated circuit die can shift its position with respect to the X-axis, or with respect to the Y-axis, or with respect to the Z-axis. This shift in position may occur while the volatile material in the epoxy based glue is vaporizing. The misalignment between the integrated circuit die and the copper pattern on the substrate after cure is normally about plus or minus fifty microns (50 μm) in the X direction and in the Y direction. The integrated circuit die may also tilt up or down in the Z direction as much as fifty microns (50 μm). The misalignment caused by the curing process is also a major source of error in the placement of an integrated circuit die. There can be a cumulative misalignment of as much as one hundred fifty microns (150 μm) between the integrated circuit die and the tooling holes of the substrate.
There is therefore a need in the art for an improved system and method for aligning an integrated circuit die on an integrated circuit substrate during the manufacture of an integrated circuit package. There is also a need in the art for an improved system and method for minimizing the misalignment between an integrated circuit die and the copper pattern on a substrate during the manufacture of an integrated circuit package.